1. Field of the Invention
This invention relates to a signal delaying outputting circuit which delays an input signal by a predetermined time and amplifies the signal by current amplification to provide an output signal to be used to drive a circuit at a next stage.
2. Description of the Related Art
When an output signal of a drive circuit which amplifies an input signal by current amplification is used to drive another circuit at a next stage, normally it is required to minimize a transfer lag of a signal arising from a switching operation of the drive circuit so that the input signal may be transmitted at a high speed to the circuit at the next stage. However, depending upon the construction of the circuit at the next stage to be driven, it is sometimes preferable to receive the input signal after it is delayed by a predetermined time by the drive circuit.
One of the circuits of the type just mentioned is such an H bridge circuit for driving a motor as shown in FIG. 8. Referring to FIG. 8, the H bridge circuit 1 shown includes four transistors T1, T2, T3 and T4 and a motor 2 connected in an H bridge connection. When it is intended to rotate the motor 2 forwardly, the transistors T1 and T4 are turned on while the other transistors T2 and T3 are turned off so that electric current flows from the transistor T1 to the transistor T4 by way of the motor 2. On the contrary when it is intended to rotate the motor 2 reversely, the transistors T2 and T3 are turned on while the transistors T1 and T4 are turned off so that electric current flows from the transistor T2 to the transistor T3.
Here, if a pair of transistors in the circuit shown at upper and lower locations in FIG. 8, for example, the transistors T1 and T3, simultaneously enter into an on state upon switching in phase of the motor 2, then high through-current flows from a high voltage power source terminal V.sub.DD to a low voltage power source terminal V.sub.SS, resulting in occurrence of such a bad effect that noise is produced or the power dissipation is increased. In order to prevent this, normally the timing at which each of a pair of upper and lower transistors is turned on is delayed with respect to the timing at which the other of the transistors is turned off so that they may not exhibit an on-state at a time. This similarly applies to the case wherein metal oxide semiconductor field effect transistors (MOS FETs) are employed in place of the transistors T1, T2, T3 and T4.
Such a signal delaying outputting circuit as shown in FIG. 9 is conventionally employed as a drive circuit whose output signals provide such different timings as described above. Referring to FIG. 9, the signal delaying outputting circuit 3 shown includes a complementary MOS (CMOS) invertor circuit at a first stage including a p-channel MOS FET 4P1 and an n-channel MOS FET 4N1, and a CMOS invertor at a second stage including a p-channel MOS FET 4P2 and an n-channel MOS FET 4N2. The dead time of the signal delaying outputting circuit 3 for delaying an input signal is provided by transmission delaying operations of the CMOS invertor circuits at the two stages.
With the signal delaying outputting circuit 3, however, since the transmission delaying operation of the gate of each MOS FET has a temperature characteristic, the dead time is liable to be varied by the temperature. Particularly at a high temperature, such a problem that the transmission delay time becomes so long that the switching time goes out of a specification set therefor sometimes occurs.
One of countermeasures to improve the problem is disclosed, for example, in Japanese Patent Laid-Open Application No. 62-224117. The circuit disclosed in the document is shown in FIG. 10. Referring to FIG. 10, the circuit includes a CMOS invertor circuit 6 including a p-channel MOS FET 5P1 and an n-channel MOS FET 5N1, and an auxiliary drive circuit 9 interposed between an output terminal 7 of the CMOS invertor circuit 6 and a ground terminal V.sub.SS and including an n-channel MOS FET 8N1 and an n-channel MOS FET 8N2. In the circuit, the resistance between the output terminal 7 and the ground terminal V.sub.ss, which is provided by the two MOS FETs 8N1 and 8N2, varies in response to the temperature of the circuit to compensate for the outputting capacity from the output terminal 7 of the terminal to prevent the turn-off time of the CMOS invertor circuit 6 from being increased remarkably at a high temperature. It is to be noted that the two MOS FETs 5P1 and 5N1 of the CMOS invertor circuit 6 are connected to receive a signal from an input terminal 12 by way of a pair of invertor circuits 10 and 11 which serve as amplification stages, respectively.
With the circuit construction of FIG. 10, however, since the turn-off time is controlled in response to a temperature variation only by the single CMOS invertor circuit 6 at the last stage, the following problem is involved where it is intended to drive the gates of MOS FETs of an H bridge circuit connected to the next stage to the circuit. In particular, referring to FIG. 10, in order to prevent the p-channel MOS FET 5P1 and the n-channel MOS FET 5N1 of the CMOS invertor circuit 6 from being simultaneously turned on to cause through-current to flow through the circuit, when the output from the output terminal 7 changes in level from a HIGH level to a LOW level, it is necessary, for example, to advance turning off and retard turning on of the p-channel MOS FET 5P1. To this end, the ratio W/L between the gate width W and the gate length L of a MOS FET which constitutes the invertor circuit 10 at the preceding stage to the p-channel MOS FET 5P1 must be made considerably high, and the value of the ratio W/L increases as the capacitances of the MOS FETs constituting the H bridge circuit increase. Since the capacitances of MOS FETs constituting an H bridge circuit for driving a motor are generally high, the gate width W of the MOS FET constituting the invertor circuit 10 is on the order of several thousands .mu.m. Accordingly, the circuit construction shown in FIG. 10 is disadvantageous in that the chip area is comparatively large.